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Logic Design and Verification
4 Years - 5 Months

Job Description

1. Good experience in the Logic Design/Verification team. 2. This position requires at least 4yrs of relevant industry experience. 3. Candidate will be involved in logic design and developing Testbench for the Block / Cluster, Testcases, Testplans and Functional as well as Code coverage. 4. Candidate will work on verification of complex SoCs / IPs and provide technical leadership to the team. 5. Candidate will develop expertise in multiple areas of verification, RTL, power aware simulations, drive verification closure, timing closure, formal verification and equivalence checking on complex modules using SystemVerilog/UVM based methodology. Skills Required: 1. Good understanding of ASIC design, verification concepts, techniques and process from test plan to coverage completion. 2. Prior Experience of verification of complex SoCs / IPs in a leading role in multiple areas of verification, RTL, power aware simulations, drive verification closure, timing closure, formal verification and equivalence checking on complex modules using SystemVerilog/UVM based methodology. 3. Strong Hands-On experience with Verilog/System Verilog and UVM/OVM/VMM. 4. Experience in project planning, resource allocation, scheduling and status reporting. 5. Should be a good mentor and guide for junior engineers in the team. 6. Minimum 4 years of experience in Logic Design/Verification

Skills
System Verilog, Axi, UVM

Education
BE

Contact Person:
Gayathri

Regards,
Gayathri
9148443449
Gayathri.d@prathigna.co.in

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